硬件体系结构：2025–2026 年度综述

An annual survey of the cs.AR arXiv category, covering research published from September 2025 – August 2026. Built on a close-reading set of 100 papers and organised into 36 chapters, it maps the year by the field's research sub-directions.

Book framework (share of the year's output):

• Algorithm-Hardware Co-Design for Energy-Efficient Accelerators (58.7%) — This subdirection focuses on co-designing algorithms and hardware architectures to improve energy efficiency and performance across diverse workloads, including neural networks, genome analysis, and stochastic computing.
• Large Language Model Inference Acceleration and Optimization (39.2%) — This subdirection addresses the hardware and architectural challenges of accelerating large language model (LLM) inference, including memory optimization, precision scaling, and specialized accelerator design.
• Reconfigurable and In-Memory Computing for Matrix Operations (0.7%) — This subdirection explores FPGA-based and in-memory computing architectures for accelerating matrix multiplication and other linear algebra operations, often with analog or reconfigurable components.
• Data Movement and Precision in Cloud-Scale Computing (0.7%) — This subdirection tackles the bottlenecks of data movement, bandwidth, and arithmetic precision in large-scale cloud and data center environments, including floating-point format standardization.
• Fundamental Bottlenecks in Emerging Computing Paradigms (0.3%) — This subdirection identifies and addresses critical scalability and performance challenges in conventional and emerging computing architectures, such as thermal management and interconnect limits.
• Heterogeneous Integration for Power and Latency Constraints (0.2%) — This subdirection investigates heterogeneous 3D integration and packaging technologies to meet power, latency, and area constraints in real-time and high-performance systems.
• Analog and Memristive Computing for Specialized Applications (0.1%) — This subdirection examines the use of analog and memristive devices for accelerating specific applications, such as neural network guidance and solving differential equations.
• Communication-Aware Acceleration for Graph and Distributed Workloads (0.1%) — This subdirection focuses on designing hardware and compiler techniques to reduce communication overhead in graph processing and distributed neural network workloads.

Each sub-direction is covered across three chapters — how it framed its questions, the strength of its key findings, and its open debates and frontiers — so the reader gets a traceable picture of what this part of the field actually produced over the year.